Apply for 3rd National FPGA [Electronic Hardware] Design Competition-2018

Kathmandu, July 11, 2016: 3^rd National FPGA Design Competition 2018 is going to be organized at July 14, 2018 (Ashad 30, 2075) at Kathford Int’l College of Engineering and Management, Balkumari, Lalitpur. The Competition is jointly organized by Kathford Int’l College of Engineering and Management and Digitronix Nepal Pvt. Ltd.

The objective of the Contest is promoting the FPGA Development Technology/Skills from contest in Nepal, enhancing the FPGA research and development environment in Nepal, exploring skills and opportunities on FPGA and hardware design to Students and Professionals in Nepal.

The first winner of the contest will get cash prize of NRs. 20,000 and 10,000 by second winner and 7000 by third winner along with Xilinx ZedBoard FPGA training module. All the participants will get certification for participation. Winner and some of selected participants will get internships from Digitronix Nepal in cooperation with Xilinx University Program Centers at different engineering college of Nepal.

The timelines of the contest are as follows

1. Registration Last Date :July 10, 2018 (Ashad 26,2075)
2. Pre Project Demonstration : July 11, 2018 (Ashad 27, 2075)
3. Final Demonstration and Prize Distribution: Saturday, July 14, 2018 (Ashad 30,2075)

In the pre demonstration round participants will have short demonstration and Jury will select some of the project for the final round. Final demonstration round till cover the demonstration, presentation and questions/answer sessions on the project. The judgment jury will finalize three projects based on hardware resource utilization, optimization, and operation/function of the project. The prize distribution will be carried out on the same day by the honored guest from Institute of Engineering, Tribhuvan University.

This is the third FPGA Design Competition in Nepal while First was organized at 2016 & second was organized at 2017 by Digitronix Nepal and Engineering colleges. This event will have two categories of themes one is Basic design with combinational and sequential circuits and another is advance design consists of Finite State Machine Design, peripheral interfacing, Robotics and Case study type of design in FPGA.

The contestant can participate on the following themes,

1. Basic Design

1. 1. Combinational Logic – Shifter,  ALU design etc.
   2. Sequential Logic – RAM design, Serial Access Memory, Content Addressable memory etc.
   3. The combination of Both Logic: Counter, Shift Register etc.

1. Advance Design

1. 1. Finite State Machine:

• Moore Machine, Mealy Machine, Door Controller, Elevator Controller, Traffic Controller , Sequence Detector, Vending Machine etc.

1. 1. Peripherals interfacing :

• UART, HDMI, VGA, Timer, SDCard, SPI , I2C,RTC,ADC,PWM, USB, Ethernet, Display, Touch Displays etc.

1. 1. Robotics:

• Line tracking, object detection , alarming , Multimedia streaming, Human detection etc.

1. 1. Case Study:

• Answering Machine, Voting Machine , Face Detection etc.

The Registration of the contest is open until July 11 [Final Extended Deadline]. Registration is Free. Individual contestant and team up to 4 members can apply for the contest. For Registration, here is the registration form link: Contest Form

All of the Participants will get “Certification of Participation” and Winners will get prizes with “Winner Certificate”. Those who participate and interested in working on FPGA Research and Development then selected of them will get opportunities with internships at Digitronix Nepal and Xilinx University Program Centers at IOE Pulchowk Campus, Himalaya College of Engineering, Kathford Int’l College of Engineering and Management, Sagarmatha Engineering College and Kantipur Engineering College.

According to Deepesh Man Shakya , FPGA Design Expert, Xilinx Inc. Ireland “ The Design Contest will enhance the FPGA design skills of enthusiasts in Nepal  with latest technologies and competitiveness”. Krishna Gaihre, Contest Coordinator, Digitronix Nepal, thinks that this contest will push the research initiatives on FPGA design and development environment to next level/edge.

For any queries and confusions for participation, organizer will be available at: Contact Email  and contact number: +977-9841078525.