Kathmandu, July 15, 2018: Arjun Neupane from Nepal Engineering College wins 3rd National FPGA Design Competition 2018 for his project – “16-bit Microprocessor Design, Simulation and Implementation”. The winner was also awarded a cash prize of NRs. 15,000.
The first runner-up was Ms. Shweta Chaudhary, Kala Raut and Ichchha Rauniyar from Khwopa Engineering Campus with the project traffic light design and prototype for Baneswor Chowk, and the second runner-up, Mr. Subash Pandey from IOE Thapathali Campus with the project Vehicle Number Plate Recognition, received Rs. 7,000 and Rs. 4000 respectively.
The award winners will also get an opportunity to receive training on Xilinx Zynq FPGA development board and Internship on FPGA research and development at Digitronix Nepal. The competition also get request from the international participant’s from Indian Institute of Technology (IIT)-India & some university students from USA, in the upcoming competition organizer will also include those international request for the participation on FPGA Design Competition.
An advisor of this event Mr. Deepesh Man Shakya, a Xilinx FPGA Engineer said this 3rd edition of FPGA Design Competition is a major milestone in introducing and enhancing FPGA education in Nepal and provide a platform for creating FPGA based research and development centers. Mr. Shakya said such initiatives could potentially turn into a design house providing hi-tech engineering jobs to many aspiring engineers within the country.
Dr. Madhusudan Kayastha , Principal of Kathford International College of Engineering and Management suggested to participant for preparing research papers and articles which will help then for further courier. The co-ordinator of this competition Mr. Krishna Gaihre from Digitronix Nepal & LogicTronix said that there has been a huge interest from engineering colleges and students towards FPGA Research and Development. Digitronix Nepal is currently focused on training, research and development of hardware designs based on FPGA. Digitronix Nepal also believes that within few years it will be create 10s of opportunities for Nepalese Engineering Graduates on the field of FPGA Design & VLSI Design.
The chief guest at the event Prof. Dr. Dinesh Kumar Sharma from IOE Pulchowk Campus lauded the event organizers and supporters for the effort they have put and also expressed his support in adopting FPGA in the mainstream engineering courses and help develop FPGA research environment in engineering colleges in Nepal.
The competition was jointly organized by Kathford Int’l College of Engineering and Management, Digitronix Nepal Pvt. Ltd and LogicTronix. The total of 10 teams participate in the competition.
FPGA, a short form for Field Programmable Gate Array, is a programmable chips technology widely used in hardware systems such as mobile phones, cars to applications in space missions.
